Object-oriented programming is a dominant software development paradigm in the industry today, and has been so for the last decade. The notion of an object as a real-world abstraction that represents an entity and its supported methods appeals for developing clean, extensible and modular software in today's rapidly evolving codebase. On the other hand, the evolution in memory system architecture has been largely stagnant, with address-based schemes being the norm and indirection being the popular form of hardware abstraction to the software. But the widening gap between the performance of the CPU and the memory, the cost of indirection, and low hardware intelligence has made object-oriented software less efficient than raw imperative programs, making them less appealing to build production quality code.
On the other hand, the semiconductor industry is moving into unchartered territory with transistor feature sizes scaling down to a few atoms and reaching the threshold limits of Moore's Law. The impact of the scaling limits will be seen most heavily in Dynamic Random Access Memory (DRAM) technology since the DRAM uses the minimum sized transistors to build a memory array and is most reliant on process scaling to provide denser and higher capacity memory systems. Therefore, DRAM designers are trying to propose alternative technologies and architectures to ensure that the cost per bit of the new memory system remains the same while guaranteeing reasonable performance compared to existing DRAM. Emerging Non-Volatile Memory (NVM) technologies, like Phase Change Memory (PCM), Spin-Transfer Torque Magnetic RAM (STT-MRAM), Resistive RAM (RRAM), etc., are largely seen as the alternative solution to solve the gap in the performance and the cost per bit in the memory and storage stack.
With the emergence of new NVM technologies with faster random access and scope for byte-level granularity, the separation between the memory and storage has considerably thinned. Coupled with the growth of Big Data applications in modern datacenters, there is a need to rethink the way the hardware interface is designed to access memory and storage. The inefficiencies mainly arising due to the mismatch in the way software objects are handled by the hardware, and the multiple layers of indirection posed by the Virtual Memory and the File System interface, need to be addressed to build a fast scalable unified memory and storage.